[Synth 8-434] mixed level sensitive and edge triggered event controls are not supported for synthesis 【错误代码行】 always @ ( clk_i or posedge rst_i ) 【错误原因】 因为一个触发器不能同时是边缘触发和电平触发的，因此不可被综合。所以直接去掉rst信号。 always @ ( clk_i ) 或者是边沿触发 always @ ( posedge clk_i or posedge rst_i )
[Synth 8-27] event control except as first statement of always block not supported ["":703]： 【错误代码行】 @(negedge clk_i); stackoverflow 上解释： You must note that delays (regular or timing based) are not supported in RTL coding. (RTL means synthesizeable i.e., the code can be implemented on hardware) Your code will simulate but do not get synthesized.(Will give the error you specified) Try removing the @(posedge clk) inside your block. You won’t get the error. 【解决办法】删掉这一行
repeat 不可综合问题 用count代替
以#开头的延时不可综合成硬件电路延时，综合工具会忽略所有延时代码，但不会报错。 如：a=#10 b; 这里的#10是用于仿真时的延时，在综合的时候综合工具会忽略它。即综合的时候上式等同于a=b;
