Verilog实现FIR滤波器

1、FIR滤波器简介

不追究FIR滤波器的深层含义，我们只关注如何实现；可以看出，FIR滤波器的本质就是延迟、系数相乘与求和，如下图：

 

2、设计

基于以上分析，按照三级流水实现FIR滤波器设计：信号延迟-系数相乘-求和

`timescale 1ns / 1ps module fir( input clk, input rst_n, input [3:0]din, output reg [9:0]dout ); // data reg reg [3:0]din1; reg [3:0]din2; reg [3:0]din3; reg [3:0]din4; reg [3:0]din5; reg [3:0]din6; reg [3:0]din7; // mul reg [7:0]mul1; reg [7:0]mul2; reg [7:0]mul3; reg [7:0]mul4; reg [7:0]mul5; reg [7:0]mul6; reg [7:0]mul7; // coffe parameter COEFF1 = 4'b0001; parameter COEFF2 = 4'b0001; parameter COEFF3 = 4'b0001; parameter COEFF4 = 4'b0001; parameter COEFF5 = 4'b0001; parameter COEFF6 = 4'b0001; parameter COEFF7 = 4'b0001; always@(posedge clk or negedge rst_n) begin if(!rst_n) begin din1 <= 4'b0000; din2 <= 4'b0000; din3 <= 4'b0000; din4 <= 4'b0000; din5 <= 4'b0000; din6 <= 4'b0000; din7 <= 4'b0000; mul1 <= 7'd0; mul2 <= 7'd0; mul3 <= 7'd0; mul4 <= 7'd0; mul5 <= 7'd0; mul6 <= 7'd0; mul7 <= 7'd0; end else begin din1 <= din;//延时部分 din2 <= din1; din3 <= din2; din4 <= din3; din5 <= din4; din6 <= din5; din7 <= din6; mul1 <= din1<<COEFF1;// 系数相乘部分 mul2 <= din2<<COEFF2; mul3 <= din3<<COEFF3; mul4 <= din4<<COEFF4; mul5 <= din5<<COEFF5; mul6 <= din6<<COEFF6; mul7 <= din7<<COEFF7; dout <= mul1 + mul2 + mul3 + mul4 + mul5 + mul6 + mul7;//求和部分 end end endmodule

3、参考

有限冲激响应（FIR）滤波器 和无限冲激响应（IIR）滤波器

数字IC设计——FIR滤波器（二）（低通FIR滤波器的Verilog实现）