用verilog实现脉冲检测

代码思路和上一篇边沿检测基本一致，通过使用两个触发器，并结合逻辑组合实现检测

但要注意题目里对pulse的定义是什么，本题中pulse是指一个时钟周期宽度的窄脉冲

verilog代码：

module pulse_detector(input clk, rst_n, din, output pulse_high_detect); reg q0,q1; assign pulse_high_detect = (~din) & q0 & (~q1); always@(posedge clk, negedge rst_n) begin if(!rst_n) begin q0 <= 0; q1 <= 0; end else begin q0 <= din; q1 <= q0; end end endmodule

testbench:

`timescale 1ns/1ns module pulse_detector_tb; reg CLK,RST_N,DIN; wire PULSE_HIGH_DETECT; reg i,j; pulse_detector U_pulse_detector( .clk(CLK), .rst_n(RST_N), .din(DIN), .pulse_high_detect(PULSE_HIGH_DETECT) ); initial begin CLK = 0 ; for(i = 0 ; i<10000; i=i+1) begin #1 CLK = ~CLK; end end initial begin DIN = 0 ; for(j = 0 ; j<100; j=j+1) begin #1 DIN = 0; #1 DIN = 1; #1 DIN = 1; #1 DIN = 1; #1 DIN = 0; #1 DIN = 0; #1 DIN = 1; #1 DIN = 0; #1 DIN = 1; #1 DIN = 0; end end initial begin RST_N = 1; #5 RST_N = 0; #5 RST_N = 1; end endmodule

仿真结果：